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## Drawing VHDL Block Diagram

Enter a valid VHDL entity declaration into the input field and generate the source code of the corresponding LaTeX block diagram. Start every port declaration in a new line. Each of them includes the name of the port and its direction with a colon between them.

Pay attention to the closing semicolon of the last port.

The in ports will be on the left side, and the out and inout ports will be on the right side of the entity.

Ports will be grouped by adding newlines between them.

Adding the comment --top-- will locate the following port on the top side. Similarly, adding the comment --bottom-- will locate the following port on the bottom side. Remove all other comments from the declaration.

Clicking on Options icon will introduce two more parameters of VHDL to LaTeX Converter:

• placing the name of the entity design in the middle or at the top of the entity,
• and changing the place of the labels of the ports.

entity Comp is

generic ( n : natural := 2 );
port (

A       : in std_logic_vector(n-1 downto 0);

B       : in std_logic_vector(n-1 downto 0);

greater : out std_logic

less    : out std_logic;

--bottom--
equal   : out std_logic;

);
end Comp;
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## VHDL to LaTeX Converter

entity Comp is

generic ( n : natural := 2 );
port (

A       : in std_logic_vector(n-1 downto 0);

B       : in std_logic_vector(n-1 downto 0);

greater : out std_logic

less    : out std_logic;

--bottom--
equal   : out std_logic;

);
end Comp;
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## Changelog

= 0.0.4 =

• [Fixed] Fix case insensitive pattern matches.

= 0.0.3 =

• [Updated] Increase the number of accepted ports on both sides from 10 to 26.